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features floating channel designed for bootstrap operation fully operational to +400v tolerant to negative transient voltage dv/dt immune gate drive supply range from 10 to 20v undervoltage lockout for both channels separate logic supply range from 5 to 20v logic and power ground 5v offset cmos schmitt-triggered inputs with pull-down cycle by cycle edge-triggered shutdown logic matched propagation delay for both channels outputs in phase with inputs ir2110e4 high and low side driver product summary v offset 400v max. i o +/- 2a / 2a v out 10 - 20v t on/off (typ.) 120ns & 94ns delay matching 10ns www.irf.com 1 symbol parameter min. max. units v b high side floating supply absolute voltage -0.5 v s + 20 v s high side floating supply offset voltage ? 400 v ho high side output voltage v s -0.5 v b + 0.5 v cc low side fixed supply voltage -0.5 20 v lo low side output voltage -0.5 v cc + 0.5 v dd logic supply voltage -0.5 v ss + 20 v ss logic supply offset voltage v cc - 20 v cc + 0.5 v in logic input voltage (hin, lin & sd) v ss - 0.5 v dd + 0.5 dv s /dt allowable offset supply voltage transient (fig. 16) ? 50 v/ns p d package power dissipation @ t a = 25c (fig. 19) ? 1.6 w r thja thermal resistance, junction to ambient ? 125 c/w t j junction temperature -55 125 t s storage temperature -55 150 t l package mounting surface temperature 300 (for 5 seconds) weight 0.45 (typical) g v c absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. additional information is shown in figures 28 through 35.
the ir2110e4 is a high voltage, high speed power mosfet and igbt driver with independent high and low side referenced output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. logic inputs are compatible with standard cmos or lsttl outputs. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates up to 400 volts. pd-60086c
r2110e4 2 www.irf.com recommended operating conditions the input/output logic timing diagram is shown in figure 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at 15v differential. typical ratings at other bias conditions are shown in figures 36 and 37. symbol parameter min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage -4 400 v ho high side output voltage v s v b v cc low side fixed supply voltage 10 20 v lo low side output voltage 0 v cc v dd logic supply voltage v ss + 5 v ss + 20 v ss logic supply offset voltage -5 5 v in logic input voltage (hin, lin & sd) v ss v dd symbol parameter min typ. max. min. max units t est conditions t on turn-on propagation delay ? 120 150 ? 260 v s = 0v t off turn-off propagation delay ? 94 125 ? 220 v s = 400v t sd shutdown propagation delay ? 110 140 ? 235 v s = 400v t r turn-on rise time ? 25 35 ? 50 c l = 1000pf t f turn-off fall time ? 17 25 ? 40 c l = 1000pf mt delay matching, hs & ls turn-on/off ? ? 20 ? ? ht on -lt on ht off -lt off typical connection hin up to 500 v to load v dd v b v s ho lo com hin lin v ss sd v cc lin v dd sd v ss v cc v dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15v, c l = 1000 pf, t a = 25c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in figure 3. tj = 25 c tj = -55 to 125 c /
ir2110e4 www.irf.com 3 symbol parameter min typ. max. min. max units t est conditions v ih logic ?1? input voltage 9.5 ? ? 10 ? v dd = 15v v il logic ?0? input voltage ? ? 6 ? 5.7 v dd = 15v v oh high level output voltage, v bias - v o ? 0.7 1.2 ? 1.5 v in = v ih , i o = 0a v ol low level output voltage, vo ? ? 0.1 ? 0.1 v in = v il , i o = 0a i lk offset supply leakage current ? ? 50 ? 250 v b = v s = 400v i qbs quiescent v bs supply current ? 125 230 ? 500 v in = v ih or v il i qcc quiescent v cc supply current ? 180 340 ? 600 v in = v ih or v il i qdd quiescent v dd supply current ? 5 30 ? 60 v in = v ih or v il i in+ logic ?1? input bias current ? 15 40 ? 70 v in = 15v i in- logic ?0? input bias current ? ? 1 ? 10 v in = 0v v bsuv+ v bs supply undervoltage positive 7.5 8.7 9.7 ? ? going threshold v bsuv- v bs supply undervoltage negative 7.0 8.3 9.4 ? ? going threshold v ccuv+ v cc supply undervoltage positive 7.4 8.6 9.6 ? ? going threshold v ccuv- v cc supply undervoltage negative 7.0 8.2 9.4 ? ? going threshold i o+ output high short circuit pulsed 2 ? ? ? ? v out = 0v, v in = 15v current pw < = 10 i o- output low short circuit pulsed 2 ? ? ? ? v out = 15v, v in = 0v current pw < = 10 static electrical characteristics v bias (v cc , v bs , v dd ) = 15v, t a = 25c and v ss = com unless otherwise specified. the v in , v th and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. tj = 25c tj = -55 to 125c v v a a s s
r2110e4 4 www.irf.com figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions figure 3. shutdown waveform definitions sd t sd ho lo 50% 90% hin lin t r t on t f t off ho lo 50% 50% 90% 90% 10% 10% hin lin ho 50% 50% 10% lo 90% mt ho lo mt 4 8 15 11 13 14 17 2 1 9 6 4
ir2110e4 www.irf.com 5 figure 9b. shutdown time vs. voltage figure 8a. turn-off time vs. temperature figure 8b. turn-off time vs. voltage figure 7a. turn-on time vs. temperature figure 7b. turn-on time vs. voltage figure 9a. shutdown time vs. temperature 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply voltage (v) turn-on delay time (ns) max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) turn-on delay time (ns) max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) turn-off delay time (ns) max. typ. 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply voltage (v) turn-off delay time (ns) max. typ. 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply voltage (v) shutdown delay time (ns) max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) shutdown delay time (ns) max. typ.
r2110e4 6 www.irf.com figure 12a. logic ?1? input threshold vs. temperature figure 12b. logic ?1? input threshold vs. voltage figure 10a. turn-on rise time vs. temperature figure 11a. turn-off fall time vs. temperature figure 11b. turn-off fall time vs. voltage figure 10b. turn-on rise time vs. voltage 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) turn-on rise time (ns) max. typ. 0 20 40 60 80 100 10 12 14 16 18 20 v bias supply voltage (v) turn-on rise time (ns) max. typ. 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature (c) turn-off fall time (ns) max. typ. 0 10 20 30 40 50 10 12 14 16 18 20 v bias supply voltage (v) turn-off fall time (ns) max. typ. 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature (c) logic "1" input threshold (v) min. 0.0 3.0 6.0 9.0 12.0 15.0 5 7.5 10 12.5 15 17.5 20 v dd logic supply voltage (v) logic "1" input threshold (v) min.
ir2110e4 www.irf.com 7 figure 13a. logic ?0? input threshold vs. temperature figure 13b. logic ?0? input threshold vs. voltage figure 14a. high level output vs. temperature figure 14b. high level output vs. voltage figure 15b. low level output vs. voltage figure 15a. low level output vs. temperature 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature (c) logic "0" input threshold (v) max. 0.0 3.0 6.0 9.0 12.0 15.0 5 7.5 10 12.5 15 17.5 20 v dd logic supply voltage (v) logic "0" input threshold (v) max. 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) high level output voltage (v) max. 0.00 0.20 0.40 0.60 0.80 1.00 -50 -25 0 25 50 75 100 125 temperature (c) low level output voltage (v) max. 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply voltage (v) high level output voltage (v) max. 0.0 3.0 6.0 9.0 12.0 15.0 5 7.5 10 12.5 15 17.5 20 v dd logic supply voltage (v) logic "1" input threshold (v) min.
r2110e4 8 www.irf.com figure 16b. offset supply current vs. voltage figure 16a. offset supply current vs. temperature figure 18a. v cc supply current vs. temperature figure 18b. v cc supply current vs. voltage figure 17a. v bs supply current vs. temperature figure 17b. v bs supply current vs. voltage 0 125 250 375 500 625 10 12 14 16 18 20 v cc fixed supply voltage (v) v cc supply current ( a) max. typ. 0 125 250 375 500 625 -50 -25 0 25 50 75 100 125 temperature (c) v cc supply current (a) max. typ. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature (c) v bs supply current ( a) max. typ. 0 100 200 300 400 500 10 12 14 16 18 20 v bs floating supply voltage (v) v bs supply current ( a) max. typ. 0 100 200 300 400 500 0 100 200 300 400 500 v b boost voltage (v) offset supply leakage current ( a) max. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature (c) offset supply leakage current ( a) max.
ir2110e4 www.irf.com 9 figure 21a. logic ?0? input current vs. temperature figure 21b. logic ?0? input current vs. voltage figure 19a. v dd supply current vs. temperature figure 19b. v dd supply current vs. voltage figure 20a. logic ?1? input current vs. temperature figure 20b. logic ?1? input current vs. voltage 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) v dd supply current ( a) max. typ. 0 20 40 60 80 100 5 7.5 10 12.5 15 17.5 20 v dd logic supply voltage (v) v dd supply current ( a) max. typ. 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) logic "1" input bias current ( a) max. typ. 0 20 40 60 80 100 5 7.5 10 12.5 15 17.5 20 v dd logic supply voltage (v) logic "1" input bias current ( a) max . typ. 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) logic "0" input bias current ( a) max. 0.00 1.00 2.00 3.00 4.00 5.00 5 7.5 10 12.5 15 17.5 20 v dd logic supply voltage (v) logic "0" input bias current ( a) max.
r2110e4 10 www.irf.com 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v cc undervoltage lockout + (v) max. typ. min. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v bs undervoltage lockout + (v) max. typ. min. figure 22. v bs undervoltage (+) vs. temperature figure 23. v bs undervoltage (-) vs. temperature figure 24. v cc undervoltage (+) vs. temperature figure 25. v cc undervoltage (-) vs. temperature figure 26a. output source current vs. temperature figure 26b. output source current vs. voltage 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v bs undervoltage lockout - (v) max. typ. min. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v cc undervoltage lockout - (v) max. typ. min. 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply voltage (v) output source current (a) min. typ. 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) output source current (a) min. typ.
ir2110e4 www.irf.com 11 figure 28. ir2110 t j vs. frequency (irfbc20) r gate = 33w, v cc = 15v figure 29. ir2110 t j vs. frequency (irfbc30) r gate = 22w, v cc = 15v figure 27b. output sink current vs. voltage figure 27a. output sink current vs. temperature figure 31. ir2110 t j vs. frequency (irfpe50) r gate = 10w, v cc = 15v figure 30. ir2110 t j vs. frequency (irfbc40) r gate = 15w, v cc = 15v 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply voltage (v) output sink current (a) min. typ. 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) output sink current (a) min. typ.
r2110e4 12 www.irf.com figure 32. ir2110s t j vs. frequency (irfbc20) r gate = 33w, v cc = 15v figure 33. ir2110s t j vs. frequency (irfbc30) r gate = 22w, v cc = 15v figure 36. maximum v s negative offset vs. v bs supply voltage figure 37. maximum v ss positive offset vs. v cc supply voltage figure 34. ir2110s t j vs. frequency (irfbc40) r gate = 15w, v cc = 15v figure 35. ir2110s t j vs. frequency (irfpe50) r gate = 10w, v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v -10.0 -8.0 -6.0 -4.0 -2.0 0.0 10 12 14 16 18 20 v bs floating supply voltage (v) v s offset supply voltage (v) typ. 0.0 4.0 8.0 12.0 16.0 20.0 10 12 14 16 18 20 v cc fixed supply voltage (v) v ss logic supply offset voltage (v) typ.
ir2110e4 www.irf.com 13 functional block diagram lead symbol description v dd logic supply hin logic input for high side gate driver output (ho), in phase sd logic input for shutdown lin logic input for low side gate driver output (lo), in phase v ss logic ground v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return lead definitions v b sd lin v dd pulse gen r s q v ss uv detect delay hv level shift v cc pulse filter uv detect v dd /v cc level shift v dd /v cc level shift lo v s com r s q r s rq hin ho
r2110e4 14 www.irf.com case outline and dimensions ? leadless chip carrier (lcc-18) package ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 ir leominster : 205 crawford st., leominster, massachusetts 01453, usa tel: (978) 534-5776 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . data and specifications subject to change without notice. 05/2011

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